1.1. Logic Gates
2.2. EXPERIMENT 1 – Half Adder
In Table 1, A and B are the two inputs of half adder, and S and C are the two outputs of half adder, S is the sum bit and C is the carry bit.
From the Table 1, we can get Boolean algebra of half adder
If only NAND gate is available, we should change the form of the Boolean algebra as follows
And then, we can get block diagram of half adder.
3.3. EXPERIMENT 2 – Full Adder
3.1.4 Experiment Lecture
3.1.5 Experiment Report
Finish the following questions:
- Required Questions:
Question 4.1.1 Attention: The circuit diagram refers to a diagram that contains 7400 ICs, connections between pins and wires. That means how to implement a Half Adder using workbench which you did in the laboratory.
Question 4.2.1 Attention: The same as Question 4.1.1.
- Optional Questions:
3.1.6 Report Format and Deadline
- Report Format: electrical document, .doc/.docx/.pdf will be OK.
- Deadline: Before the end of this semester.
- Mailbox: firstname.lastname@example.org
Attention: You would get zero for your experiment if you didn’t send the report to me before the deadline or to the right mailbox.
3.1.7 Contact Me
If you have any question, please leave a message below this passage or send me an email, I will be pleasure to help you.